Aggregate-predistortion: Power amplifier pre-distortion with low power consumption, high precision, low latency and low complexity
Domaines
Sécurité
Mobilité
Numérique
Technologie Infrastructures de 5ème génération
Challenges
Digital communication techniques, such as OFDM and carrier aggregation, are dramatically improving the spectral efficiency of communications in response to their exponential growth. However, these techniques generate signals that are sensitive to power amplifier (PA) non-linearities. These reduce the quality of the useful signal and cause spectral bleed-back into adjacent communication channels. To remedy these problems, a powerful linearization technique is digital pre-distortion (DPD). It minimizes distortion and enables PAs to operate more linearly and efficiently.
We propose a new DPD method based on low-latency adaptive filtering, up to 10 times faster than the speed of conventional algorithms, and low complexity with 12% fewer operations.
Innovative Solution
Algorithm to reduce power amplifier non-linearities with 10 times faster convergence and 12% lower power consumption.
APPLICATIONS
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Adaptive filtering
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Amplifier linearization
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Broadband radio-frequency circuits
AVANTAGES
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10 times faster convergence
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12% energy savings
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State-of-the-art power amplifier linearization
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Compatible with all power amplifier technologies
How it works ?
In DPD, an inverse model (predistorter) of the amplifier is computed using a least square algorithm (LMS). One way to reduce the computation time is by decreasing the complexity and improving the convergence speed of these algorithms that calculate the predistorter terms. LMS/RLS methods have a scalar approach to data processing, while other comparable algorithms (Block LMS) utilize a vector approach to enhance their performance at the expense of hardware resources.
Our technology aims to reduce the computational cost of a Block LMS by combining it with a Walsh Transform (WLMS). This approach allows the computation of predistorter coefficients in this mathematical basis, taking advantage of the fast convergence speed of a Block LMS at a lower cost.


Inventeurs
François RIVET, Yann DEVAL, Hervé LAPUYADE et Maxandre FELLMAN :
Integration from Material to Systems laboratory (IMS)
(université de Bordeaux, CNRS, Bordeaux-INP)
Propriété intellectuelle
A patent filed : WO/2024208899
DEVELOpMENT : TRL 2/3
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Start of circuit manufacturing in October 2023.
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Manufacturing of a chip by April 2024.
Contact
Benoît SORE
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